Title :
A 5.42nW/kB retention power logic-compatible embedded DRAM with 2T dual-Vt gain cell for low power sensing applications
Author :
Lee, Yoonmyung ; Chen, Mao-Ter ; Park, Junsun ; Sylvester, Dennis ; Blaauw, David
Author_Institution :
Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8× longer retention time, 5× lower refresh power and 30% reduced area compared with the lowest power eDRAM previously reported. With an area-efficient single inverter sensing scheme designed for R/W speed compatibility with ultra-low power processors, 58% array efficiency is maintained for memories as small as 2kb and for as few as 32 bits per bitline.
Keywords :
DRAM chips; low-power electronics; logic-compatible embedded DRAM; low power sensing applications; ultra-low power processors; ultra-small sensing systems; Arrays; Inverters; Random access memory; Sensors; Subthreshold current; Time measurement; Transistors;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
DOI :
10.1109/ASSCC.2010.5716635
