Sequential logic optimization based on state space decomposition

Binary decision diagrams (BDDs) and implicit state enumeration have provided remarkable improvements to sequential logic synthesis, testing, and verification in recent years. However, their inability to deal with large circuits has been the major limitation of the methods based on them. A method to compute a subset of unreachable states using implicit state enumeration, which can be applied to large circuits where the current exact methods fail is presented. Since it is guaranteed that the computed unreachable state set is contained in the exact unreachable state set, this set can be used as invalid state don´t cares in sequential logic optimization. Traversal and optimization results on benchmark examples are provided