ESD Protection Design by Using Only 1Ã\x97VDD Low-Voltage Devices for Mixed-Voltage I/O Buffers with 3Ã\x97VDD Input Tolerance

Author

Ker, Ming-Dou ; Wang, Chang-Tzu

Author_Institution

Nat. Chiao-Tung Univ., Hsinchu

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

287

Lastpage

290

Abstract

A new electrostatic discharge (ESD) protection design by using only 1timesVDD low-voltage devices for mixed-voltage I/O buffer with 3timesVDD input tolerance is proposed. A special ESD detection circuit has been proposed to improve ESD protection efficiency of ESD clamp device by substrate-triggered technique to achieve high ESD level. This design has been successfully verified in a 0.13-mum CMOS process to provide an excellent circuit solution for on-chip ESD protection in the mixed-voltage I/O buffers with 3timesVDD input tolerance.

Keywords

CMOS integrated circuits; buffer circuits; electrostatic discharge; CMOS process; ESD clamp; ESD detection circuit; ESD protection design; VDD low-voltage devices; electrostatic discharge protection; input tolerance; mixed-voltage I/O buffers; on-chip ESD protection; size 0.13 micron; substrate-triggered technique; Circuits; Clamps; Diodes; Electrostatic discharge; MOS devices; Protection; Stress; Thyristors; Variable structure systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357907

Filename

4197646