A fast heuristics for optimal CMOS functional cell layout generation

The problem of generating minimal-area CMOS functional cell layout can be converted to that of decomposing the transistor connection graph into a minimum number of subgraphs, each having a pair of Euler paths, with the same sequence of input labels on the N-graph and P-graph, which are portions of the graph corresponding to NMOS and PMOS parts, respectively. The authors propose a heuristic algorithm which yields a nearly minimum number of Euler paths from the path representation formulation which represents the given logic function. Subpath merging is done through a list processing scheme where the pairs of paths that results in the lowest cost are successively merged from all candidate merge pairs until no further path merging and no further reduction of the number of subgraphs are possible.<>