A 0.6-V, 6.8-μW Embedded SRAM for Ultra-low Power SoC

Author

Sohn, Kyomin ; Choi, Sungdae ; Woo, Jeong-Ho ; Kim, Jooyoung ; Yoo, Hoi-Jun

Author_Institution

Dept. of Electron. Eng. & Comput. Sci., Daejon

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

315

Lastpage

318

Abstract

A novel embedded SRAM is proposed with features of high reliability and low power consumption. The critical control signals are made in correspondence to clock-duty cycle for high reliability. A hybrid precharge scheme is adopted for low power consumption. Additionally, an asymmetric read-write scheme is useful in a slow-but-steady write situation such as a control SoC for BSN (body sensor network). The fabricated 128-kb embedded SRAM consumes 117-μW at the worst case and 6.8-μW at normal write operation in a 0.6-V supply voltage.

Keywords

SRAM chips; integrated circuit reliability; low-power electronics; system-on-chip; asymmetric read-write scheme; body sensor network; clock-duty cycle; embedded SRAM; high reliability; hybrid precharge scheme; low power consumption; power 6.8 μW; slow-but-steady write situation; storage capacity 128 Kbit; ultra-low power SoC; voltage 0.6 V; Body sensor networks; Clocks; Delay estimation; Energy consumption; Pulse width modulation inverters; Random access memory; Signal generators; Space vector pulse width modulation; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357914

Filename

4197653