Title :
Functional verification for retiming and rebuffering optimization
Author :
Kostelijk, A.P. ; van der Werf, A.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
An algorithm which proves or disproves functional consistency of a sequential datapath after a combination of retiming, pipelining and buffering optimizations is presented. The verification algorithm is complete and efficient. It includes verification of external latency constraints. Experiments have confirmed the speed of the implemented algorithm and errors were clearly indicated in industrial designs
Keywords :
data flow graphs; formal verification; logic design; sequential circuits; external latency constraints; functional consistency; functional verification; logic timing analyser; pipelining; rebuffering optimization; retiming; sequential datapath; verification algorithm; Algorithm design and analysis; Circuits; Clocks; Clustering algorithms; Delay; Design optimization; Laboratories; Latches; Pipeline processing; Runtime;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386493
