Title :
A 10-b 100-MS/s 95mW CMOS ADC IP With Emphasis on Layout Matching
Author :
Wang, Nan ; Zhou, Ping
Author_Institution :
Shanghai Hua Hong NEC Electron. Co. Ltd, Shanghai
Abstract :
This paper describes the design of a 10-b 100-Msamples/s pipelined ADC IP fabricated in a 0.25-um CMOS process with MIM capacitor option. The IP core is implemented with 1.5-b/stage structure, amplifier sharing technique, and swing-improved telescopic OTA design to achieve amplitude of 2.4 V-pp at power supply range from 2.7 V to 3.6 V, dissipating only 95 mW at 3.0 V. For 10.7 MHz input, it achieves 58.8dB SNR, 69.0 dB SFDR and 66.5 dB THD. With the proposed capacitor matching layout, the ADC achieves excellent differential nonlinearity of-0.174 ~ +0.210 LSB.
Keywords :
CMOS integrated circuits; MIM structures; analogue-digital conversion; integrated circuit layout; operational amplifiers; CMOS ADC IP; CMOS process; IP core; MIM capacitor option; amplifier sharing technique; capacitor matching layout; differential nonlinearity; frequency 10.7 MHz; layout matching; pipelined ADC IP; power 95 mW; size 0.25 mum; swing-improved telescopic OTA design; voltage 2.7 V to 3.6 V; word length 10 bit; Bandwidth; CMOS process; Capacitors; Clocks; Energy consumption; National electric code; Power amplifiers; Sampling methods; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
Conference_Location :
Hangzhou
Print_ISBN :
0-7803-9734-7
Electronic_ISBN :
0-7803-97375-5
DOI :
10.1109/ASSCC.2006.357924
