Methods for automatic design error correction in sequential circuits

Author

Fujita, Masahiro

Author_Institution

Fujitsu Laboratories Ltd., Kawasaki, Japan

fYear

1993

fDate

22-25 Feb 1993

Firstpage

76

Lastpage

80

Abstract

Given two circuits, one specification and the other design, a correspondence between states of the two circuits is first assumed or the circuits are expanded by several time frames. Based on that correspondence or expansion, the proposed methods try to automatically correct design errors by changing the part of the circuit which is specified by a designer. Experimental results show that the proposed method can be a very effective tool for FSM designs where small manual design modifications may happen frequently

Keywords

error correction; finite state machines; formal verification; logic CAD; sequential circuits; state assignment; Boolean unification procedure; FSM designs; automatic design error correction; finite state machines; formal verification; logic design errors; patching state machines; sequential circuits; Binary decision diagrams; Counting circuits; Design methodology; Error correction; Formal verification; Laboratories; Logic design; Sequential circuits; State-space methods; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Conference_Location

Paris

Print_ISBN

0-8186-3410-3

Type

conf

DOI

10.1109/EDAC.1993.386497

Filename

386497