• DocumentCode
    256126
  • Title

    Fast incremental 3D full-wave analysis for package-board design iterations via eigen-GCR

  • Author

    Chatterjee, G. ; Das, A. ; Gope, D.

  • Author_Institution
    Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
  • fYear
    2014
  • fDate
    14-16 Dec. 2014
  • Firstpage
    25
  • Lastpage
    28
  • Abstract
    In a typical design cycle many iterations on the package-board-system layout may be performed to meet design specifications. In the process, the analysis step needs to be repeated as many times as the number of layout variants. The cost of analysis, especially if using a 3D fullwave extraction methodology, therefore becomes prohibitive for large-scale analysis in the design process. In this paper, a methodology is proposed to expedite analysis of subsequent layout iterations based on information stored from previous layout solution. The efficiency of a Method of Moments (MoM) based 3D full-wave solution is limited by the slow convergence of the iterative solver in a fast solver framework. In this work, eigen-vectors from a previously solved layout is used to augment to the Krylov subspace to expedite the convergence of a Generalized Conjugate Residual (GCR)-based iterative solution for next layout. Numerical results demonstrate up to 40% improvement in the convergence properties using the proposed GCR method.
  • Keywords
    chip-on-board packaging; convergence of numerical methods; eigenvalues and eigenfunctions; integrated circuit layout; iterative methods; method of moments; 3D fullwave extraction methodology; Krylov subspace; MoM; eigen-GCR method; eigen-vectors; fast incremental 3D full-wave analysis; generalized conjugate residual method; iterative solver convergence; method of moments; package-board design iterations; package-board-system layout; Conductors; Convergence; Layout; Linear systems; Method of moments; Three-dimensional displays; Vectors; Generalized Conjugate Residual (GCR); Iterative solver; Power integrity; Signal Integrity;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2014 IEEE
  • Conference_Location
    Bangalore
  • Type

    conf

  • DOI
    10.1109/EDAPS.2014.7030806
  • Filename
    7030806