• DocumentCode
    25613
  • Title

    IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures

  • Author

    Junghee Lee ; Nicopoulos, C. ; Hyung Gyu Lee ; Panth, Shreepad ; Sung Kyu Lim ; Jongman Kim

  • Author_Institution
    Georgia Inst. of Technol., Atlanta, GA, USA
  • Volume
    21
  • Issue
    6
  • fYear
    2013
  • fDate
    Jun-13
  • Firstpage
    1080
  • Lastpage
    1093
  • Abstract
    Imbalanced distribution of workloads across a chip multiprocessor (CMP) constitutes wasteful use of resources. Most existing load distribution and balancing techniques employ very limited hardware support and rely predominantly on software for their operation. This paper introduces IsoNet, a hardware-based conflict-free dynamic load distribution and balancing engine. IsoNet is a lightweight job queue manager responsible for administering the list of jobs to be executed, and maintaining load balance among all CMP cores. By exploiting a micro-network of load-balancing modules, the proposed mechanism is shown to effectively reinforce concurrent computation in many-core environments. Detailed evaluation using a full-system simulation framework indicates that IsoNet significantly outperforms existing techniques and scales efficiently to as many as 1024 cores. Furthermore, to assess its feasibility, the IsoNet design is synthesized, placed, and routed in 45-nm VLSI technology. Analysis of the resulting low-level implementation shows that IsoNet´s area and power overhead are almost negligible.
  • Keywords
    microprocessor chips; multiprocessing systems; queueing theory; CMP; IsoNet; VLSI technology; chip multiprocessor; conflict-free dynamic load distribution; hardware-based job queue management; lightweight job queue manager; load balancing; many-core architectures; micronetwork; size 45 nm; Computer architecture; Hardware; Instruction sets; Load management; Parallel processing; Job queue; load balancing; many-core; multicore;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2012.2202699
  • Filename
    6243223