DocumentCode
2561330
Title
A High Speed VLSI Architecture of SPIHT without Lists for Real-Time Applications
Author
Liu, Kai ; Lei, Jie ; Li, Yunsong
Author_Institution
Sch. of Comput. Sci. & Technol., Xidian Univ., Xi´´an, China
fYear
2010
fDate
23-25 Sept. 2010
Firstpage
1
Lastpage
4
Abstract
In this paper, we present a bit-plane parallel architecture for a modified SPIHT without lists algorithm using the breadth first search for coefficient trees. This scheme can ensure that the quality of reconstructed images is almost the same with that of SPIHT with lists. Compared with the other architectures, our architecture has advantages of high parallelism, no intermediate buffer and ability to error resilience as the coefficient trees are visited independently.
Keywords
buffer storage; image coding; image reconstruction; tree searching; SPIHT; bit-plane parallel architecture; breadth first search; buffer; error resilience; high speed VLSI architecture; image reconstruction; real-time applications; Computer architecture; Encoding; Hardware; Image coding; Logic gates; Pixel; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Communications Networking and Mobile Computing (WiCOM), 2010 6th International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-3708-5
Electronic_ISBN
978-1-4244-3709-2
Type
conf
DOI
10.1109/WICOM.2010.5601029
Filename
5601029
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