DocumentCode
2561411
Title
Efficiency improvement for slicing point placements
Author
Thio, P.E.
Author_Institution
Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
fYear
1993
fDate
22-25 Feb 1993
Firstpage
34
Lastpage
39
Abstract
A package implemented for floorplan optimization is discussed. It contains algorithms for finding optimal sliced rectangle dissections consistent with initial data structures such as point placements, partitioning trees, slicing trees, and floorplans. Among these point slicing achieves relatively high area utilization. Although the worst-case time complexity of the algorithm is polynomial in the number of rectangles (O (n 6)), average case time and memory usage is high. A strategy to reduce these complexities while keeping a near-optimal solution likely is introduced. Also a selection of more wirable dissections among those with equal contour score is presented
Keywords
circuit layout CAD; circuit optimisation; integrated circuit layout; algorithms; efficiency improvement; floorplan optimization; optimal sliced rectangle dissections; package; partitioning trees; relatively high area utilization; slicing point placements; slicing trees; time complexity; wireability; Data structures; Geometry; Packaging; Partitioning algorithms; Shape; Tree data structures;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location
Paris
Print_ISBN
0-8186-3410-3
Type
conf
DOI
10.1109/EDAC.1993.386504
Filename
386504
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