Title :
An integrated algorithm for optimal floorplan sizing and enumeration
Author :
Yeap, Kok-Hoo ; Sarrafzadeh, Majid
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
Abstract :
A generalized optimal sizing problem on a set of related slicing trees is considered. For computation efficiency, the tree enumeration and sizing process are combined in a unified algorithm where floorplan trees and cell sizes are computed simultaneously. The tree enumeration is based on a dual graph of the input cells, which ensures that the adjacency requirements of the cells are preserved. Experimental results using MCNC benchmarks are reported
Keywords :
circuit layout CAD; circuit optimisation; integrated circuit layout; trees (mathematics); MCNC benchmarks; computation efficiency; dual graph; input cells; integrated algorithm; optimal floorplan sizing; slicing trees; tree enumeration; Cost function; Linear programming; Partitioning algorithms; Polynomials; Tree graphs;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386505
