A Wide-Range Burst Mode Clock and Data Recovery Circuit

Author

Chen, Wei-Zen ; Wei, Chin-Yuan ; Chen, Jen-Wen

Author_Institution

Nat. Chiao-Tung Univ., Hsin-Chu

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

403

Lastpage

406

Abstract

This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 mum CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10^-10.

Keywords

CMOS digital integrated circuits; clocks; limiters; phase detectors; phase locked loops; synchronisation; CMOS process; bang-bang phase detector; binary-search phase acquisition; bit rate 0.625 Gbit/s to 3.125 Gbit/s; burst mode receiver; data recovery circuit; demultiplexer circuit; dynamic loop filter; limiting amplifier; power 78 mW; rapid phase locking; size 0.18 mum; wide-range burst mode clock; Bandwidth; Circuits; Clocks; Detectors; Digital filters; Jitter; Phase detection; Phase locked loops; Sampling methods; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357936

Filename

4197675