Implementation aspect of MIMO decoder

Wireless communication systems are dense compositions of signal processing and VLSI technologies. Due to increase in demand of higher data rate and better quality of services, VLSI design and implementation method for wireless communication becomes more challenging. Multiple-input and multiple-output (MIMO) technique is rapidly increasing in the last decade which provides higher throughput at no additional cost of bandwidth, but the high complexity of the detection method is the major challenge to the hardware implementation. The computational complexity grows exponentially with the number of transmit and receive antenna used in the MIMO system. This paper presents an FPGA prototyping of the MIMO decoder with a detailed description of the design and implementation. The results are obtained for 2×2 MIMO systems by decoding at the receiver.