DocumentCode
2562329
Title
The Named-State Register File: implementation and performance
Author
Nuth, Peter R. ; Dally, William J.
Author_Institution
Hewlett-Packard Co., Palo Alto, CA, USA
fYear
1995
fDate
1995
Firstpage
4
Lastpage
13
Abstract
Context switches are slow in conventional processors because the entire processor state must be saved and restored, even if much of the state is not used before the next context switch. This paper introduces the Named-State Register File, a fine-grain associative register file. The NSF uses hardware and software techniques to efficiently manage registers among sequential or parallel procedure activations. The NSF holds more live data per register than conventional register files, and requires much less spill and reload traffic to switch between concurrent contexts. The NSF speeds execution of some sequential and parallel programs by 9% to 17% over alternative register file organizations. The NSF has access time comparable to a conventional register file and only adds 5% to the area of a typical processor chip
Keywords
cache storage; file organisation; parallel architectures; program compilers; software performance evaluation; storage allocation; storage management; access time; concurrent contexts; fine-grain associative register file; hardware techniques; named-state register file; parallel procedure activations; register file organization; reload traffic; sequential procedure activations; software techniques; Artificial intelligence; Costs; Hardware; Laboratories; Milling machines; Program processors; Registers; Switches; Traffic control; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Computer Architecture, 1995. Proceedings., First IEEE Symposium on
Conference_Location
Raleigh, NC
Print_ISBN
0-8186-6445-2
Type
conf
DOI
10.1109/HPCA.1995.386560
Filename
386560
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