A sub 2W low power IA processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

This presentation describes a low power Intel Architecture (IA) processor specifically designed for Mobile Internet Devices. The design relies on high residency in a new low-power state in order to keep average power and idle power below 220 and 80 mW, respectively. The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32KB instruction and 24KB data L1 caches, independent integer and floating point execution units, ×86 front end execution unit, a 512KB L2 cache with in-line ECC and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus. The design contains 47 million transistors in a die size under 25 mm2 manufactured in a 9-metal 45nm CMOS process with optimized transistors for low leakage. Several circuit techniques to reduce dynamic and leakage power will be presented. Maximum thermal design power consumption is measured at 2W at 1.0V, 90C using a synthetic power-virus test at a frequency of 1.86GHz.