Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Author

Wang, Chang-Tzu ; Ker, Ming-Dou ; Tang, Tien-Hao ; Su, Kuan-Cheng

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2009

fDate

18-20 May 2009

Firstpage

21

Lastpage

24

Abstract

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7 kV human-body-model (HBM) and 325 V machine model (MM) ESD tests which occupying an silicon area of only 49 mum times 21 mum and consuming a very low standby leakage current of 96 nA at room temperature.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit technology; thyristors; CMOS process; CMOS technology; ESD detection circuit; SCR device; complementary metal-oxide-semiconductor integrated circuits; current 96 nA; gate current; human-body-model; low leakage electrostatic discharge protection circuit; low leakage power-rail electrostatic discharge clamp circuit; machine model; power-rail ESD clamp circuit; silicon controlled rectifiers; size 65 nm; standby leakage current; voltage 325 V; voltage 7 kV; CMOS process; CMOS technology; Circuit testing; Clamps; Electrostatic discharge; Fabrication; Leak detection; Leakage current; Protection; Thyristors; Electrostatic discharge (ESD); gate leakage; power-rail ESD clamp circuit; silicon controlled rectifier (SCR);

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-2933-2

Electronic_ISBN

978-1-4244-2934-9

Type

conf

DOI

10.1109/ICICDT.2009.5166256

Filename

5166256