Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating

Dual-edge-triggered flip-flop (DETFF) allows us to use half the clock frequency while maintaining the same throughput, thereby cutting the clock power in half. DETFF-based design, however, requires multiple runs of timing analysis, which is critical for short turn-around time; to make it worse, the number of analysis increases if we use clock gating and multiple clock gating logic, both of which are typical in practical designs. Alternative approach is to perform analysis once assuming the tightest timing condition, which turns out to be too pessimistic. Timing analysis method for DETFF-based circuit with clock gating is proposed for the first time. The method is based on identifying a cluster of nets that have to be associated with multiple required arrival times (RATs); the remaining nets having a single RAT then can be processed by conventional timing analysis. Experiments with several benchmark circuits in 65-nm technology demonstrate that, at 50% point of cumulative slack histogram, the slack from our analysis was 1.78times on average of the slack from conventional timing analysis assuming the tightest timing condition, and 1.30times at 90% point.