Implementation of area efficient H.264/AVC CAVLC decoder

In this paper, we propose the VLSI architecture of H.264/AVC CAVLC Decoder which is able to reduce power consumption by using area-efficient method. In the proposed architecture, we reduce the lookup table area by rearranging the entries of lookup tables. We also save the bus area and processing cycles consumed decoding T1s by decoding T1s value at the final reordering step which is performed in output buffer. We can find overlapped logics between the controller and barrel shifter. To remove the overlapped logics, we combine a controller and a barrel shifter. By using these proposed methods, we can reduce the area and power consumption by about 30% and 15% separately compared with previous works. We design the proposed decoder using Verilog HDL and synthesize it using 0.35 mum standard cell library. We verify the proposed architecture by simulation that the designed decoder can run at the frequency of 50 MHz.