Title :
Systematic approach of FinFET based SRAM bitcell design for 32nm node and below
Author :
Song, S.C. ; Abu-Rahma, M. ; Han, B.M. ; Ge, L. ; Yoon, S.S. ; Wang, J. ; Yang, W. ; Liu, D. ; Hu, C. ; Yeap, G.
Author_Institution :
Qualcomm Inc., San Diego, CA, USA
Abstract :
Methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves considerations on both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower Vccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell < 0.1 mum2 below 32 nm node.
Keywords :
MOSFET; SRAM chips; integrated circuit design; Fin configuration; FinFET bitcell; SRAM bitcell design; size 32 nm; Degradation; Design methodology; Electrostatics; FinFETs; Leakage current; Manufacturing; Optimization methods; Random access memory; Stability; Threshold voltage; 22nm; 32nm; Bitcell; FinFET; Icell; MuGFET; SNM; SRAM; Vccmin;
Conference_Titel :
IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-2933-2
Electronic_ISBN :
978-1-4244-2934-9
DOI :
10.1109/ICICDT.2009.5166287
