Title :
Towards fabrication of Vertical Slit Field Effect Transistor (VeSFET) as new device for nano-scale CMOS technology
Author :
Barbut, Lucian ; Bouvet, Didier ; Sallese, Jean-Michel
Abstract :
This paper proposes a CMOS based process for Vertical Slit Field Effect Transistors. The central part of the device, namely, the vertical slit, is defined by using electron beam lithography and silicon dry etching. In order to verify the validity and the reproducibility of the process, devices having the slit width ranging from 16 nm to 400 nm were fabricated, with slit conductance in the range 0.6 to 3 milliSiemens, in agreement with the expected values.
Keywords :
CMOS integrated circuits; electron beam lithography; etching; field effect transistors; nanoelectronics; nanofabrication; electron beam lithography; nanoscale CMOS technology; silicon dry etching; size 14 nm to 400 nm; vertical slit field effect transistor fabrication; Dry etching; FETs; Fabrication; Logic gates; Resists; Silicon; VESTIC; VeSFET; electron beam lithography; nanoelectronic device; vertical slit;
Conference_Titel :
Semiconductor Conference (CAS), 2011 International
Conference_Location :
Sinaia
Print_ISBN :
978-1-61284-173-1
DOI :
10.1109/SMICND.2011.6095805
