Compact 6T SRAM cell with robust read/write stabilizing design in 45nm Monolithic 3D IC technology

This paper presents an innovative 6T SRAM cell designed in Monolithic 3D IC technology. A specific compact model in 45 nm has been developed haled on silicon measurements and TCAD extractions. The simulation results exhibit a strong improvement of the cell electrical characteristics thanks to the ability to modulate the threshold voltage of the devices (static noise margin +10%, number of bit per line +12%, static power consumption -12%), when compared with a standard 6T cell designed in 2D. The cell layouts, designed with 45 nm SRAM rules in 2D and 3D, show a 20% area gain.