Performance Guarantees for Flow-Mapping Parallel Packet Switch

Flow-mapping parallel packet switch (FM-PPS) is the class of parallel packet switch adopting flow-level load-balancing algorithms. It dispatches packets of a micro-flow into an unchanged parallel switch, thus natively guarantees intra-flow packet orders. Due to the heavy tail of flow size distribution, it is concerned that FM-PPS may suffer from unpredictable performance which prevents it from real deployments. Motivated to clarify this issue, in this paper, we present an effective analytical model on FM-PPS and carry out intensive performance analysis. We find that under current Internet traffic patterns, both statistical packet delay and backlog bounds can be guaranteed if only several stability conditions are met. We further validate that a FM-PPS with OC-768c line rate is able to provide such guarantees under state-of-the-art RAM technology. A practical flow-mapping algorithm, namely constrained output round robin (CORR), is also proposed, which is designed to conform to these stability conditions, hence holds the delay and backlog bound.