Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization

Leakage power is a major concern in current microarchitectures as it is increasing exponentially with decreasing transistor feature sizes. In this paper, we present a technique called functional unit shutdown to reduce the static leakage power consumption of a microprocessor by power gating functional units when not used. We use profile information to identify functional unit idle periods that is used by the compiler to issue corresponding OFF/ON instructions. The decision to power gate during idle periods is made based on the comparison between the energy consumed by leaving the units ON and the overhead and leakage energy involved in power cycling them. This comparison identifies short idle periods where less power is consumed if a functional unit is left ON rather than cycling the power during that period. The results show that this technique saves up to 18% of the total energy and between 4 and 11% on average with a performance degradation of 1%.