A CMOS Batcher and banyan chip set for B-ISDN

Batcher and banyan chips that are suitable for broadband packet switch applications, simultaneously accommodate 32-bit serial packet channels, and are building blocks for larger networks are discussed. 1.2- mu m CMOS Batcher and banyan chips were tested at bit rates of 170 Mb/s. The chips require a single 5-V supply, dissipate approximately 1.5 W, provide 5.44-Gb/s switching capacity, and are packaged in 84-pin leadless ceramic chip carriers (LCC) for conventional testing. An N-input by an N-output (N*N) Batcher or banyan network is a rectangular array of identical 2*2 processing elements (cells). A processing element can take on one of two states. Each network accomplishes distributed processing over serial bit streams. The bit streams are network binary output addresses presented most significant bit first. The algorithm executed by a given network depends on the state determination logic of the 2*2 elements, as well as on the wiring permutations between successive columns in the array. Batcher networks sort packets according to output address, whereas banyan networks deliver packets to their desired output address.<>