Title :
A 40 MIPS (peak) 64-bit microprocessor with one-clock physical cache load/store
Author :
Miyake, Jun ; Maeda, T. ; Nishimichi, Y. ; Katsura, J. ; Tainguchi, T. ; Yamaguchi, Satarou ; Edamatsu, H. ; Watari, S. ; Takagi, Yutaka ; Tsuji, Keita ; Kuninobu, S. ; Cox, Shane ; Duschatko, D. ; MacGregor, D.
Author_Institution :
Matsushita Semicond. Res. Center, Osaka, Japan
Abstract :
A 64-b RISC (reduced-instruction-set-computer) microprocessor that performs a load/store instruction in one clock and achieves 40 MIPS and 20-MFLOPS peak performance at 40 MHz clock is described. Two techniques are used to attain this performance: (1) two translation lookaside buffers (TLBs) with parallel and hierarchical word-line transition detection circuits; (2) a self-clocked register file using a data-flow clocking scheme. A floating-point unit performs single- and double-precision floating-point operations concurrently with an integer unit. The chip is fabricated using 0.8- mu m double-metal CMOS technology. About 1M transistors are contained in the 14.85*15. 13-mm die housed in a 238-pin pin-grid array (PGA).<>
Keywords :
CMOS integrated circuits; clocks; microprocessor chips; reduced instruction set computing; 0.8 micron; 20 MFLOPS; 40 MIPS; 64 bits; RISC; data-flow clocking scheme; double-metal CMOS technology; floating-point unit; one-clock physical cache load/store; pin-grid array; self-clocked register file; translation lookaside buffers; word-line transition detection circuits; CMOS technology; Circuits; Clocks; Data buses; Delay; Error correction; Memory management; Microprocessors; Reduced instruction set computing; Registers;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110120
