Title :
A mainframe processor in CMOS technology with 0.5 mu m channel length
Author :
Schettler, H. ; Hajdu, J. ; Getzlaff, K. ; Loehlein, W.-D. ; Starke, C.-W.
Author_Institution :
IBM Lab., Boeblingen, Germany
Abstract :
A prototype of a processor chip set with a mainframe architecture is implemented using five CMOS standard cell chips. High performance is achieved by wide buses and a RISC- (reduced-instruction-set-computer) like implementation of frequently used instructions. The chip set consists of four units: (1) an instruction processor chip which fetches and decodes the instructions and contains the microcode storage; (2) cache chips which contain the address translation for up to 19 virtual address spaces, a four-way set-associative 16-kByte data/instruction cache, and a 32-B instruction buffer, which is loaded 16 B/cycle from the cache; (3) a fixed-point processor chip which contains the fixed-point registers and arithmetic and a second adder for the address calculation (base+displacement+index); (4) a floating-point processor chip which contains the floating-point registers, multiplier, and arithmetic unit. The processor is based on a four-stage pipeline (five stages for floating-point instructions).<>
Keywords :
CMOS integrated circuits; cellular arrays; microprocessor chips; parallel architectures; pipeline processing; reduced instruction set computing; 16 kB; 32 B; CMOS technology; RISC; cache chips; channel length; fixed-point processor chip; floating-point processor chip; four-stage pipeline; instruction buffer; instruction processor chip; mainframe architecture; processor chip set; standard cell chips; virtual address spaces; Buffer storage; CMOS process; CMOS technology; Cache storage; Decoding; Fixed-point arithmetic; Floating-point arithmetic; Pipelines; Prototypes; Registers;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110124
