Title :
A 200 k gate 0.8 mu m mixed CMOS/BiCMOS sea-of-gates
Author :
Enomoto, Yoshihide ; Sasaki, T. ; Tsutsumi, Shinichi ; Tone, S.
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
Abstract :
The key features of a mixed CMOS/BiCMOS sea-of-gates are given. They are (1) 207 K basic cells in mixed CMOS/BiCMOS structure using only 6 % more cell area than a pure CMOS structure; (2) 400-ps delay for a two-input NAND with F/O=1 achieved by 0.8- mu m BiCMOS technology; (3) RAM and ROM configurable with up to 18-kb RAM, 64-kb ROM; (4) emitter-coupled-logic interface for data transfer at above 100 MHz, as well as a transistor-transistor logic interface.<>
Keywords :
BIMOS integrated circuits; CMOS integrated circuits; cellular arrays; integrated logic circuits; 0.8 micron; 18 kbit; 400 ps; 64 kbit; ECL interface; ROM configurable; emitter-coupled-logic interface; mixed CMOS/BiCMOS; sea-of-gates; transistor-transistor logic interface; BiCMOS integrated circuits; Epitaxial layers; Flip-flops; MOS devices; MOSFETs; Propagation delay; Substrates;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110144
