DocumentCode :
2565248
Title :
A 200 MIPS image signal multiprocessor on a single chip
Author :
Maruyama, Mihoko ; Nakahira, H. ; Araki, Takeshi ; Sakiyama, S. ; Kitao, Y. ; Aono, K. ; Yamada, Hiroyoshi
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
fYear :
1990
fDate :
14-16 Feb. 1990
Firstpage :
122
Lastpage :
123
Abstract :
An image signal multiprocessor (ISMP) that is composed of four processor elements (PEs) and a main controller and is designed for general-purpose local image processing or feature extraction is described. The processor uses parallel processing and a CMOS process providing integration density 10 times larger than that of a bipolar process. As a result, it operates at 200 MIPS with a 12-b precision. The ISMP has 300 K transistors on a 14.4*13.7-mm chip fabricated with 1.2- mu m double-metal CMOS process technology and is mounted in 176-pin grid array. The power dissipation is 2.9 W from a single 5-V power supply. Four PEs are the most suitable tradeoff between speed and integration level. The main controller controls start of execution, data input, data output, and PE program loading. The ISMP has five image input ports accepting five vertical image data.<>
Keywords :
CMOS integrated circuits; computerised picture processing; microprocessor chips; parallel architectures; 1.2 micron; 12 bit; 2.9 W; 200 MIPS; 5 V; PGA; double-metal CMOS process; feature extraction; image signal multiprocessor; local image processing; parallel processing; pin grid array; power dissipation; power supply; Adders; CMOS process; CMOS technology; Circuits; Feature extraction; Image edge detection; Image processing; Radio frequency; Registers; Signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
Type :
conf
DOI :
10.1109/ISSCC.1990.110157
Filename :
110157
Link To Document :
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