FPGA implementation of HIHO and SIHO decoders for DSC codes

This paper presents the study of two decoder architectures and their VHDL design and implementation on a FPGA circuit. Both decoders are designed for Difference Set Cyclic (DSC) codes. The first one is the Hard In - Hard Out decoder (HIHO), and the second one is the Massey´s threshold Soft In - Hard Out (SIHO) decoder. The two architectures are analyzed and discussed for serial and parallel processing implementations. The results show that the complexity, measured by the number of Logical Elements (LE) which is directly proportional to the silicon area occupied by the decoder, varies linearly for serial processing and hyperbolically for parallel processing. Increased complexity related to parallel processing can be accepted in turbo decoders. The resulting latency (L) is equal to the code length (n) multiplied by the clock period (H): (L=n*H).