Title :
A 23 ns 4 Mb CMOS SRAM with 0.5 mu A standby current
Author :
Sasaki, Kazuhiko ; Ishibashi, Koji ; Yamanaka, T. ; Shimohigashi, K. ; Moriwaki, Nobihiro ; Honjo, S. ; Ikeda, Shoji ; Koike, Atsushi ; Meguro, Sakae ; Minato, O.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A 4-Mb (512 K*8) CMOS SRAM that uses a 0.5- mu m quadruple-poly double-metal CMOS technology to attain 23-ns address access time with a single 5-V external supply voltage and a load capacitance of 30 pF is described. Current-mirror/PMOS cross-coupled cascade sense amplifier circuits with a noise-immune data-latch circuit are used. A polysilicon PMOS load memory cell enables a 0.5- mu A standby current (V/sub cc/=3 V) with a 17- mu m/sup 2/ memory cell area. A 122-mm/sup 2/ (7.2*16.9-mm) chip is achieved by the double-array word-decoder architecture.<>
Keywords :
CMOS integrated circuits; SRAM chips; 0.5 micron; 0.5 muA; 23 ns; 30 pF; 4 Mbit; 5 V; CMOS SRAM; address access time; cross-coupled cascade sense amplifier; double-array word-decoder architecture; load capacitance; noise-immune data-latch circuit; polysilicon PMOS load memory cell; quadruple-poly double-metal CMOS; standby current; static RAM; CMOS technology; Capacitance; Circuit noise; Delay; Noise figure; Pulse amplifiers; Random access memory; Semiconductor device noise; Space technology; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110161
