8 ns CMOS 64 K*4 and 256 K*1 SRAMs

64 K*4 and 256 K*1 SRAMs with 8-ns access time and using a 1.0- mu m CMOS process are described. The circuits are designed with source-coupling techniques to achieve high-speed with small-signal swings, using only CMOS devices. A metal option permits selection of the 64 K*4 or 256 K*1 configuration. The same core architecture has also been used to generate *8 and *9 designs. One version achieves 3-ns output enable access time. SRAM speed-power ratio has traditionally been improved by array subdivision and address transition detection (ATD) to decrease current. However, for operation near 100 MHz, the advantage of ATD is diminished. The design described here removes ATD, allowing the row address to propagate statically. The resulting DC current is, countered with a strategy of (1) radically increasing array subdivisions and (2) exploiting small-signal techniques, preamplifiers, and current regulation. The core consists of 32 blocks with 128 rows and 64 columns per block.<>