A 6.5 ns 1 Mb BiCMOS ECL SRAM

Author

Maki, Y. ; Kamata, Shingo ; Okajima, Yusuke ; Yamauchi, Takashi ; Fukuma, H.

Author_Institution

Fujitsu Ltd., Kawasaki, Japan

fYear

1990

fDate

14-16 Feb. 1990

Firstpage

136

Lastpage

137

Abstract

A 256 K-word*4-b emitter-coupled-logic (ECL) RAM fabricated by means of 0.8- mu m BiCMOS technology is described. The memory has an address access time of 6.5 ns with active power dissipation of 800 mW at 80 MHz. The memory utilizes a 41- mu m/sup 2/ NMOS four-transistor memory cell, 2-row and 16-column redundancy, a wired-OR sense amplifier, and an improved ECL CMOS level converter to achieve 6.5-ns access time with an ECL 10 K interface. To improve yield for a high-density RAM, a flexible redundancy scheme is necessary. The 2-row and 16-column redundant array increases the number of usable devices at least fivefold compared with a previously reported scheme.<>

Keywords

BIMOS integrated circuits; SRAM chips; emitter-coupled logic; redundancy; 0.8 micron; 1 Mbit; 6.5 ns; 80 MHz; 800 mW; BiCMOS ECL SRAM; NMOS four-transistor memory cell; active power dissipation; address access time; emitter-coupled-logic; level converter; redundancy scheme; redundant array; static RAM; wired-OR sense amplifier; BiCMOS integrated circuits; Decoding; Delay; MOS devices; MOSFETs; Power dissipation; Random access memory; Read-write memory; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Conference_Location

San Francisco, CA, USA

Type

conf

DOI

10.1109/ISSCC.1990.110164

Filename

110164