Title :
A reconfigurable CMOS neural network
Author :
Graf, H.P. ; Henderson, Dale
Author_Institution :
AT&T Bell Lab., Holmdel, NJ, USA
Abstract :
An analog CMOS neural net with a programmable architecture containing 32 K connections is discussed. The objective of packing as large a network as possible on a chip leads to the choice of an analog approach. Analog signals are used only inside the network. All the input and output data are digital. The reconfigurable network consists of building blocks that can be joined to form various network architectures. The circuit can be programmed to implement single-layer networks or multilayer networks with binary or analog connections.<>
Keywords :
CMOS integrated circuits; analogue computer circuits; neural nets; analog CMOS neural net; multilayer networks; programmable architecture; reconfigurable network; single-layer networks; Analog computers; Circuits; Concatenated codes; Current supplies; Mirrors; Neural networks; Neurons; Registers; Switches; Wire;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110168
