Low-power hardware synthesis from TRS-based specifications

Synthesis from guarded atomic actions used for high-level descriptions of hardware designs has been shown to be a successful methodology for generating efficient designs (Arvind et al., 2004). This methodology uses CAOS (concurrent action oriented specifications) for hardware description which is based on the idea of term rewriting systems (TRS´s) (Baader and Nipkov, 1998; Hoe and Arvind, 1999). A prime example of CAOS is Bluespec where the behavior of a design is described using various guarded atomic actions. Hardware synthesis from such specifications can infer more parallelism than is possible from the traditional methods of behavioral synthesis using CDFGs (control data-flow graphs) (Gupta et al.; Chang and Pedram, 1999; Lakshminarayana et al., 1998). Hardware implementations generated from CAOS can exploit the parallelism germane in the computation and execute maximal set of actions concurrently in order to reduce the latency of the design. The concurrent execution of the actions enhances the performance of the hardware designs in terms of the delay but high power consumption may become an issue when multiple such actions are executed concurrently. Thus, there is a need to reduce power consumption during the CAOS-based synthesis. In this paper, we consider a CAOS similar to Bluespec´s model of computation and present two strategies targeting the reduction of peak power and dynamic power in designs generated from such specifications. One strategy uses the re-scheduling of the atomic actions to generate a low-power schedule whereas the other exploits the factorization as well as the re-scheduling of the actions for power reduction