A 5 V, 16 b 10 mu s differential CMOS ADC

Author

Tan, K. ; Kiriaki, S. ; de Wit, M. ; Fattaruso, J. ; Tsay, F.C.-Y. ; Matthews, W.E. ; Hester, R.

Author_Institution

Texas Instrum. Semicond. Process & Design Center, Dallas, TX, USA

fYear

1990

fDate

14-16 Feb. 1990

Firstpage

166

Lastpage

167

Abstract

A fully differential charge redistribution analog-to-digital-converter (ADC) chip fabricated in a 5-V, 1.0- mu m CMOS process that includes polysilicide-to-metal capacitors, polysilicon resistors, and low-threshold n-channel transistors is discussed. The successive-approximation ADC uses self-calibration of capacitor, gain, and offset errors. Self-correction techniques are also used to eliminate first-order common-mode error and first- and second-order capacitor voltage dependence. A comparator topology minimizes comparator offset hysteresis.<>

Keywords

CMOS integrated circuits; analogue-digital conversion; error correction; 1 micron; 10 mus; 5 V; A/D convertor; capacitor voltage dependence; comparator offset hysteresis; comparator topology; differential CMOS ADC; first-order common-mode error; fully differential charge redistribution; low-threshold n-channel transistors; polysilicide-to-metal capacitors; polysilicon resistors; self correction techniques; self-calibration; successive-approximation ADC; Calibration; Circuits; Error correction codes; MOS capacitors; Transient response; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Conference_Location

San Francisco, CA, USA

Type

conf

DOI

10.1109/ISSCC.1990.110179

Filename

110179