An 18 b 10 mu s self-calibrating ADC

A self-calibrating, 18-b, serial-output, 100-ksample/s analog-to-digital converter (ADC) which is implemented on a 24-V BiCMOS analog chip and a 5-V, 2- mu m CMOS digital chip is described. This partitioning allows a larger input signal for better dynamic range, eases the comparator design, and protects analog circuitry from digital feedthrough. The two chips are wired in a 7.6-mm-wide, 16-pin plastic dual inline package (DIP). Thirteen inter-chip bonds make up the control and data interface. The only other common connections to the logic supply and its ground return are made through separate wires for each chip. The analog chip is a charge-balancing converter consisting of an 18-b calibrated digital-to-analog converter (DAC), an auto-zeroed latching comparator, buffers for all analog inputs, and logic for the self-timed interface to the digital chip. The digital chip is a custom microcontroller which implements the calibration aid conversion algorithms, as well as the digital part of the user interface. The data path on this chip includes calibration pattern generators, a successive approximation register (SAR), elements for calculating the error terms, and RAM for storing those terms.<>