A mathematical co-processor of modular arithmetic based on a FPGA

Modern cryptographic systems of public key require multiplication and modular exponentiation of large integers represented in the range of 512 to 2048 bits. If the operations are carried out programming a traditional computer system, the time processing is quite long, because integers represented with more that 32 or 64 bits cannot be processed directly in the functional units of a general purpose CPU. In that case, it is necessary to separate the calculation in parts by developing software for arrays of integers of 32 bits. Known CAS, such as MATHEMATICA© or MAPLE© handle multiplication and modular exponentiation by creating special data types and using efficient algorithms for improving the calculation time. It is known that Montgomery algorithm for modular multiplication is one of the fastest methods for calculating a · b mod n, for large a, b and n. Through programmable devices such as FPGA´s, it is possible the implementation of digital circuits for carrying out efficiently arithmetic operations taking advantage of the intrinsic parallelism of the hardware. We present the design of a mathematical co-processor of integer arithmetic for numbers represented with 1024 bits in a FPGA. The co-processor carries out modular multiplication trough the hardware implementation of Montgomery´s algorithm, accelerating so, operations in cryptographic systems. The co-processor was integrated to a traditional computing system by means of a computer bus system.