A GaAs 1.5 Gb/s clock recovery and data retiming circuit

High-speed data communications between computers will require clock and data recovery in the 800-Mb/s-to-1.6-Gb/s frequency range. Because the transmitter clock is almost always stable (i.e., locked to a crystal), a complicated phase-locked loop (PLL) or tracking filter is not required on the receiver end. A monolithic clock recovery and data retiming chip operating at 1.5 Gb/s is described. The circuit is implemented in a 0.5- mu m GaAs D-MESFET process and uses a high dielectric constant coaxial resonator for the clock filter. The chip and filter are both packaged in a metal 14-pin dual inline housing.<>