DocumentCode
2565779
Title
A monolithic CMOS 10 MHz DPLL for burst-mode data retiming
Author
Sonntag, J. ; Leonowich, R.
Author_Institution
AT&T Bell Lab., Reading, PA, USA
fYear
1990
fDate
14-16 Feb. 1990
Firstpage
194
Lastpage
195
Abstract
A first-order digital phase locked loop (DPLL) that can acquire phase lock from the highly jittered preamble of a burst-mode, Manchester-coded, 10-Mb/s data packet using information acquired from only three transistors is described. A 16-stage delay line locked to a 10-MHz reference clock is embedded in the DPLL. This allows 3.125-ns phase steps to be generated without a high-speed clock. Implemented in a 1.75- mu m CMOS technology, the DPLL circuit occupies 4 mm/sup 2/ of silicon and consumes 125 mW from a 5-V supply.<>
Keywords
CMOS integrated circuits; data communication equipment; digital integrated circuits; phase-locked loops; synchronisation; 1.75 micron; 10 MHz; 10 Mbit/s; 125 mW; 16-stage delay line; DPLL; Manchester-coded; burst-mode data retiming; data packet; first order digital PLL; monolithic IC; phase locked loop; reference clock; CMOS technology; Circuits; Clocks; Delay lines; Detectors; Jitter; Multiplexing; Phase detection; Phase locked loops; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1990.110191
Filename
110191
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