Title :
A 4 Mb block/vector addressable three-dimensional bit map memory
Author :
Ogawa, Jun ; Masuda, Y. ; Kobayashi, Kaoru ; Nishi, Tomoki
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
Abstract :
A 256K*16 graphic memory with a three-dimensional (3-D) bit map is discussed. The memory has on-the-fly selection of addressable data organized 16*1*1 or 4*4*1 in a 3-D bit map to support image processing. This access concept makes it possible to reduce the number of memory-fetch cycles to about one-sixteenth that of conventional RAMs. This is achieved by hierarchical decoding. The chip is fabricated in a 0.7- mu m CMOS DRAM technology.<>
Keywords :
CMOS integrated circuits; DRAM chips; computer graphic equipment; decoding; 0.7 micron; 3D bit map; 4 Mbit; CMOS DRAM technology; addressable data; graphic memory; hierarchical decoding; image processing; memory-fetch cycles; three-dimensional bit map memory; Data processing; Decoding; Filtering; Graphics; Image processing; Pixel; Random access memory; Shape;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110208
