• DocumentCode
    2566644
  • Title

    A 0.9V /spl Delta//spl Sigma/ Modulator with 80dB SNDR and 83dB DR Using a Single-Phase Technique

  • Author

    Goes, João ; Vaz, Bruno ; Monteiro, Rui ; Paulino, Nuno

  • Author_Institution
    Univ. Nova de Lisboa, Lisbon
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    191
  • Lastpage
    200
  • Abstract
    A 2nd-order DeltaSigma ADC implemented in 0.18mum CMOS occupies 0.06mm2 and dissipates 0.2mW from a 0.9V supply. It achieves 80dB SNDR and 83dB DR over a 10kHz BW employing a single-phase technique to reach such performance. An amplifier-sharing scheme is proposed to improve power and area efficiency
  • Keywords
    CMOS integrated circuits; amplifiers; analogue-digital conversion; delta-sigma modulation; 0.18 micron; 0.2 mW; 0.9 V; 10 kHz; ADC; CMOS; DeltaSigma modulator; SNDR; amplifier sharing scheme; single phase technique; CMOS technology; Capacitors; Clocks; Delay; Delta modulation; Sampling methods; Switches; Switching circuits; Topology; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696048
  • Filename
    1696048
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2566644