• DocumentCode
    2566788
  • Title

    A 20Gb/s Adaptive Equalizer in 0.13/spl mu/m CMOS Technology

  • Author

    Lee, Jeyull

  • Author_Institution
    National Taiwan Univ., Taipei
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    273
  • Lastpage
    282
  • Abstract
    An adaptive equalizer incorporates a spectrum-balancing technique to achieve high speed and low power obviating the need for slicers. Fabricated in 0.13mum CMOS, this circuit achieves a 20Gb/s data rate with 14ps peak-to-peak jitter and consumes 60mW from a 1.5V supply
  • Keywords
    CMOS integrated circuits; adaptive equalisers; high-speed integrated circuits; jitter; low-power electronics; 0.13 micron; 1.5 V; 20 Gbit/s; 60 mW; CMOS technology; adaptive equalizer; jitter; spectrum balancing technique; Adaptive equalizers; Bandwidth; Boosting; CMOS technology; Capacitors; Detectors; Filters; Frequency; Rectifiers; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696057
  • Filename
    1696057
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2566788