DocumentCode :
2566903
Title :
T4 Inductance extraction and compact modeling of inductively coupled interconnects in the presence of process variations
Author :
Tan, Sheldon ; Fan, Jeffrey
Author_Institution :
Univ. of California at Riverside, Riverside
fYear :
2007
fDate :
22-25 Oct. 2007
Firstpage :
11
Lastpage :
11
Abstract :
In this tutorial, we will shed some light on an inductive extraction and compact modeling of inductively coupled interconnects, especially in the presence of unavoidable fabrication variations in the technology of 90 nm and below. The tutorial consists of two parts. The first part of the tutorial will describe the existing partial element equitant circuit (PEEC) based inductance extraction methods, and compact modeling techniques of inductively coupled interconnect circuits by means of second-order model order reduction techniques. For the inductive extraction part, we will review the concepts of partial inductances, PEEC extraction methods and latest susceptance-based inductance extraction and modeling. For the inductive modeling part, we will review the existing second-order model order reduction techniques and present the latest balanced truncation based second order model order reduction techniques. The second part of this tutorial will present a few of existing modeling and simulation approaches of interconnect circuits in the presence of process variations. We will review the latest model order reduction techniques of interconnects considering process variations. Those approaches include the parametric model order reduction by multi-dimension moment matching, interval-valued based reduction approaches, the sampling space based reduction methods and the statistical spectrum based approaches. We will give several specific examples for statistical spectrum based approaches and compare them with some existing approaches.
Keywords :
VLSI; high-speed integrated circuits; inductance; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; reduced order systems; sampling methods; PEEC extraction methods; balanced truncation; design methodology; higher density VLSI integrated circuits; higher-speed integrated circuits; inductance extraction; inductively coupled interconnects modeling; interval-valued based reduction approaches; multidimension moment matching; parametric model order reduction; partial element equitant circuit; partial inductances; process variations; sampling space based reduction methods; second-order model order reduction techniques; statistical spectrum based approach; susceptance-based inductance extraction; Bandwidth; Coupling circuits; Crosstalk; Design methodology; Inductance; Integrated circuit interconnections; Integrated circuit modeling; Packaging; Skin effect; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
Type :
conf
DOI :
10.1109/ICASIC.2007.4415552
Filename :
4415552
Link To Document :
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