DocumentCode
2566942
Title
High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s Crossbar
Author
Yamada, J. ; Adachi, H. ; Mori, Yojiro ; Harada, Atsushi ; Okada, Shogo ; Ando, Hideki
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
343
Lastpage
352
Abstract
A 170GB/S crossbar for a multiprocessor server is realized with 10 LSIs. High density and low power are achieved with a 1.333 Gb/s single-ended signal transmission, a driver using pre-emphasis, and a receiver using a data-synchronous scheme. The total bandwidth of the address crossbar LSI is 1.23Tb/s with 704 drivers and 352 receivers
Keywords
large scale integration; microprocessor chips; multiprocessing systems; 1.23 Tbit/s; 1.333 Gbit/s; 170 Gbit/s; LSI; crossbar; data synchronous scheme; drivers; high-speed interconnect; multiprocessor server; receivers; single-ended signal transmission; Backplanes; Bandwidth; Clocks; Delay lines; Detectors; Feedback loop; Phase detection; Sampling methods; Transceivers; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696065
Filename
1696065
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