DocumentCode :
2566997
Title :
A self-control structure for pipeline control
Author :
Mingjun Fan ; Tingqian Chen ; Wenjing Yin ; Lei Wang ; Ning Li ; Ren, Jinchang
Author_Institution :
Fudan Univ., Shanghai
fYear :
2007
fDate :
22-25 Oct. 2007
Firstpage :
24
Lastpage :
27
Abstract :
This paper describes a 1.8-V, 8-bit, 125 Msample/s analog-to-digital converter (ADC) with a power-efficient architecture designed in a 0.18-mum CMOS technology. Through sharing an amplifier between two successive pipeline stages, the converter is realized with just three amplifiers and a separate sample-and-hold block. It employs a wide-bandwidth low-power wide-swing gain-boosting folded-cascode amplifiers, an improved bootstrap switch technique and appropriate scaling down skill. The simulation result shows the ADC achieves 57.7 -dB spurious free dynamic range (SFDR), 48- dB signal-to-noise ratio (SNR), 7.6 effective number of bits (ENOB) for 62- MHz input and consumes 36 - mw from 1.8-V supply, which also includes five buffer amplifiers.
Keywords :
CMOS integrated circuits; amplifiers; analogue-digital conversion; CMOS technology; analog-to-digital converter; bootstrap switch technique; folded-cascode amplifier; frequency 62 MHz; power-efficient architecture; size 0.18 micron; voltage 1.8 V; Circuits; Clocks; Communication system control; Digital signal processing; Performance analysis; Phase locked loops; Pipelines; Protocols; Signal generators; Timing; Handshaking protocol; self-circulation; self-control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
Type :
conf
DOI :
10.1109/ICASIC.2007.4415558
Filename :
4415558
Link To Document :
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