Design of a fully pipelined single-precision floating-point unit

Author

Li, Zhaolin ; Zhang, Xinyue ; Gongqiong Li ; Zhou, Runde

Author_Institution

Tsinghua Univ., Beijing

fYear

2007

fDate

22-25 Oct. 2007

Firstpage

60

Lastpage

63

Abstract

A fully pipelined single-precision floating-point unit is proposed in this paper. It is implemented in three pipeline stages. The core of this design is a multiply-add-fused unit. With the assistance of a lookup table and the control logic, it also implements floating-point division and square root operations, besides the basic addition, subtraction and multiply-add-fused operations. It is modeled in VerilogHDL and synthesized in 0.18 mum CMOS technology after verification. Experiment result shows that there is only 3% time penalty compared with the traditional multiply-add-fused unit.

Keywords

CMOS digital integrated circuits; floating point arithmetic; hardware description languages; logic design; VerilogHDL; control logic; floating-point division; lookup table; multiply-add-fused unit; pipelined single-precision floating-point unit; size 0.18 micron; square root operation; Algorithm design and analysis; CMOS technology; Degradation; Delay; Hardware; Information technology; Microelectronics; Performance analysis; Pipelines; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2007. ASICON '07. 7th International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4244-1131-3

Type

conf

DOI

10.1109/ICASIC.2007.4415567

Filename

4415567