Author :
Hoya, K. ; Takashima, D. ; Shiratake, S. ; Ogiwara, R. ; Miyakawa, Takayuki ; Shiga, H. ; Doumae, S.M. ; Ohtsuki, S. ; Kumura, Yusuke ; Shuto, S. ; Ozaki, Takashi ; Yamakawa, Kiyoshi ; Kunishima, I. ; Nitayama, A. ; Fujii, Shohei
Abstract :
A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst
Keywords :
CMOS memory circuits; high-speed integrated circuits; random-access storage; 0.13 micron; 200 Mbit/s; 60 ns; 64 Mbit; BL-BL coupling noise; CMOS technology; FeRAM; burst mode; cell data write back scheme; high speed ECC circuit; quad-BL architecture; read-write cycle time; CMOS technology; Capacitors; Circuit noise; Coupling circuits; Energy consumption; Error correction codes; Ferroelectric films; Noise reduction; Nonvolatile memory; Random access memory;
