• DocumentCode
    2567212
  • Title

    A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode

  • Author

    Hoya, K. ; Takashima, D. ; Shiratake, S. ; Ogiwara, R. ; Miyakawa, Takayuki ; Shiga, H. ; Doumae, S.M. ; Ohtsuki, S. ; Kumura, Yusuke ; Shuto, S. ; Ozaki, Takashi ; Yamakawa, Kiyoshi ; Kunishima, I. ; Nitayama, A. ; Fujii, Shohei

  • Author_Institution
    Toshiba, Yokohoma
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    459
  • Lastpage
    466
  • Abstract
    A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst
  • Keywords
    CMOS memory circuits; high-speed integrated circuits; random-access storage; 0.13 micron; 200 Mbit/s; 60 ns; 64 Mbit; BL-BL coupling noise; CMOS technology; FeRAM; burst mode; cell data write back scheme; high speed ECC circuit; quad-BL architecture; read-write cycle time; CMOS technology; Capacitors; Circuit noise; Coupling circuits; Energy consumption; Error correction codes; Ferroelectric films; Noise reduction; Nonvolatile memory; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696078
  • Filename
    1696078
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2567212