A design flow for clock controller hard-macro generation

This paper demonstrates a design flow for the generation of a clock controller hard-macro used in SOC design. The flow is implemented automatically with EDA tools as well as by manual and it solves the problems most SOC designs may meet such as synchronization, clock gating design, divided clock and clock tree synthesis. A clock controller hard-macro is created with the design flow and then the hard-macro is used in the design of a SOC chip. Results from post-simulations and taped-out chips have proven the validity of the flow. The design flow can also be used freely in other hard-macro generations with only a little change.